{"id":9515,"date":"2026-05-03T12:05:06","date_gmt":"2026-05-03T10:05:06","guid":{"rendered":"https:\/\/felusch.de\/?p=9515"},"modified":"2026-05-20T10:21:58","modified_gmt":"2026-05-20T08:21:58","slug":"praezision-im-netzwerk-audio-over-ip-als-signalquelle-fuer-line-array-lautsprecher-systeme","status":"publish","type":"post","link":"https:\/\/felusch.de\/en\/praezision-im-netzwerk-audio-over-ip-als-signalquelle-fuer-line-array-lautsprecher-systeme\/","title":{"rendered":"Network Precision | Audio-over-IP as a Signal Source for Line Array Speaker Systems"},"content":{"rendered":"<h4 class=\"wp-block-heading\"><em>Acoustic coherence in the field of tension between waveguide mechanics and network synchronization.<br><\/em><\/h4>\n\n\n\n<p><em>v1.<\/em>1.1. |&nbsp;<em>2026-04-28<\/em> |&nbsp;<em>\u00a9 Bodo Felusch <\/em><\/p>\n\n\n\n<p class=\"has-text-align-center\">Switch language<\/p>\n\n\n\n<!-- IMPORTANT! You need to have data-no-translation on the wrapper with the links or TranslatePress will automatically translate them in a secondary language. -->\n\n<div class=\"language-switcher-dropdown has-ermisch-spacing has-ermisch-borders has-ermisch-dimensions wp-block-ermisch-block-custom-language-switcher has-text-color has-black-color has-background has-white-background-color is-layout-flow wp-block-ermisch-block-custom-language-switcher-is-layout-flow\" aria-label=\"Sprache w\u00e4hlen\" id=\"wp-block-6a0e0fcdf3f63\" data-style-id=\"language-switcher-dropdown-a3c69207\" data-no-translation>\n    <svg class=\"lan_globe lan_svg\" width=\"24\" height=\"24\" viewbox=\"0 0 24 24\" fill=\"none\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\">\n<path d=\"M22 12C22 17.5228 17.5228 22 12 22M22 12C22 6.47715 17.5228 2 12 2M22 12H2M12 22C6.47715 22 2 17.5228 2 12M12 22C14.5013 19.2616 15.9228 15.708 16 12C15.9228 8.29203 14.5013 4.73835 12 2M12 22C9.49872 19.2616 8.07725 15.708 8 12C8.07725 8.29203 9.49872 4.73835 12 2M2 12C2 6.47715 6.47715 2 12 2\" stroke=\"#1E1E1E\" stroke-width=\"2.5\" stroke-linecap=\"round\" stroke-linejoin=\"round\"\/>\n<\/svg>\n\n    <!-- Current Language -->\n                <div class=\"current-language\">\n                <span class=\"language-link active\">\n                    en                <\/span>\n            <\/div>\n    \n    <!-- Dropdown Options -->\n    <div class=\"dropdown-options\">\n                        <a href=\"https:\/\/felusch.de\/wp-json\/wp\/v2\/posts\/9515\/\" class=\"language-link\">\n                    de                <\/a>\n            <\/div>\n\n    <svg class=\"lan_arrow lan_svg\" width=\"6\" height=\"5\" viewbox=\"0 0 6 5\" fill=\"none\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\">\n<path d=\"M3 5L0.5 0H5.5L3 5Z\" fill=\"#1D1B20\"\/>\n<\/svg>\n<\/div>\n\n\n<div style=\"height:100px\" aria-hidden=\"true\" class=\"wp-block-spacer\"><\/div>\n\n\n\n<p><\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"576\" src=\"https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/00_-_Header_01-1024x576.jpg\" alt=\"\" class=\"wp-image-9617\" srcset=\"https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/00_-_Header_01-1024x576.jpg 1024w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/00_-_Header_01-300x169.jpg 300w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/00_-_Header_01-768x432.jpg 768w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/00_-_Header_01-1536x864.jpg 1536w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/00_-_Header_01-18x10.jpg 18w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/00_-_Header_01-500x281.jpg 500w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/00_-_Header_01-800x450.jpg 800w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/00_-_Header_01-1280x720.jpg 1280w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/00_-_Header_01.jpg 1672w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<p><\/p>\n\n\n\n<p><br><\/p>\n\n\n\n<h4 class=\"wp-block-heading\" style=\"padding-top:var(--wp--preset--spacing--sm-16-r);padding-bottom:var(--wp--preset--spacing--xs-12-r)\"><strong>Reference: Timing Precision Requirements for Line Arrays<\/strong><\/h4>\n\n\n\n<p>The requirements for mechanical precision in line array loudspeakers are well-established. The waveguide is\nthe most precision-critical component, guiding the energy of the high-frequency drivers as coherently \u2014 i.e. as\nphase-linearly \u2014 as possible to the acoustic aperture. The race for the optimal waveguide has largely been run\nout, constrained by patent law. So why not open a new front?<\/p>\n\n\n\n<p>First, we need to establish a benchmark for the precision we are aiming for. Everything discussed below is\nevaluated at 20 kHz. We define the acceptable phase difference in the waveguide as 1\/4 of the wavelength \u2014\ni.e. a 90\u00b0 phase difference \u2014 yielding a summation result of +3 dB from two coherent sound sources at 0 dBr\neach. For mechanical construction this translates to an acceptable tolerance window of 4.3 mm across the full\noperating temperature range. Coupling between adjacent elements is excluded from this discussion; sufficient\nliterature already exists on that topic.&nbsp;<\/p>\n\n\n\n<p>An equivalent error budget at the upstream electronic level corresponds to approximately 12.5 \u00b5s of time\ndifference between two coherent signals at exactly 0 dBr. This is slightly more than one sample period at 96\nkHz, which has a duration of 10.4 \u00b5s. As a physical reference point: a temperature difference of just 1\u00b0C across\n10 m causes a propagation delay difference of approximately 51 \u00b5s \u2014 exceeding the entire electronic error\nbudget (~12.5 \u00b5s) by a factor of four. This strikingly illustrates that acoustic environmental conditions are often\nthe limiting factor in practice, not the electronics.<\/p>\n\n\n\n<p>New technologies such as beamforming \u2014 which aim to steer the directional behaviour of a line array segment\nelectronically \u2014 impose far more stringent precision requirements. This is almost certainly the reason why\nelectronically steered systems rely on fixed mechanical splay angles. When using FIR filters, the limiting factor\nat low frequencies is latency: at 96 kHz with 2048 taps, one must accept 10.6 ms of latency, with only 46.9 Hz\nof bandwidth per tap \u2014 all-pass filters can provide relief here. At high frequencies, the enclosure and drivers\nthemselves are the limiting constraint: to accurately control phase to within 180\u00b0 at 20 kHz, the physical\ntolerance must be kept below 8.5 mm.&nbsp;<\/p>\n\n\n\n<p>In short: at low frequencies, time is the limiting resource; at high frequencies, space is.<\/p>\n\n\n\n<h4 class=\"wp-block-heading\" style=\"padding-top:var(--wp--preset--spacing--sm-24-r);padding-bottom:var(--wp--preset--spacing--xs-12-r)\"><strong>Fundamentals of Synchronisation<\/strong><\/h4>\n\n\n\n<p><strong>Clock Drift<\/strong><br>Before mobile phones united us on a common time reference, free-running clocks defined our individual,\nabsolute, yet perpetually inaccurate sense of time. Mechanically constructed timepieces and quartz watches,\nfor instance, vary in their precision. Even two identical quartz watches will not remain in agreement over time.\nAssume a quartz oscillating at 32,768 Hz with a drift of \u00b110 ppm. If two such watches are both set to 00:00 on\nthe 1st of January and left running, they will show different times after just a month \u2014 they drift apart. In the\nworst case, the two clocks diverge by 1.7 seconds per day, and by 52 seconds after one month.\nAnyone who has recorded picture and sound on separate devices knows that both recorders must be\nsynchronised to maintain lip sync throughout the recording. The problem is exactly the same as with the two\nquartz watches: neither is locked to a common reference. Clock drift is a frequency offset \u2014 a mistuning of the\nrate at which the clock oscillator is supposed to run.<\/p>\n\n\n\n<p><\/p>\n\n\n\n<p><strong>Interface Jitter<\/strong><br>When two digital audio devices are operated at the same sample rate, connected digitally in series, but each\nlocked to its own internal clock, the same problem recurs \u2014 they drift apart and audible clicks begin to appear.\nA Clock Leader must be defined, and all digitally connected devices must be synchronised to it as Clock\nFollowers. In this process, the clock signal is transmitted over a physical medium, giving rise to Interface Jitter\nbetween the digital interfaces. In serial (daisy-chain) cabling, this interface jitter accumulates and corrupts the\nclock signal. To put it concisely: the clock edges smear in time, and the receiver can no longer reliably\ndistinguish between a one and a zero. The underlying causes are cable-induced errors such as impedance\nmismatch, capacitance, reflections, excessive cable length, or simply physical damage and ageing. Star-topology\nwiring helps to keep interface jitter low. A clock signal corrupted by interface jitter can be regenerated through\nre-clocking: the signal is buffered and re-generated by an internal clock that is itself synchronised to the Clock\nLeader.<\/p>\n\n\n\n<p><\/p>\n\n\n\n<p><strong>Clock Wander &amp; Clock Jitter<\/strong><br>Beyond the fundamental long-term drift that every oscillator exhibits \u2014 no matter how precise \u2014 there are\nalso short-term fluctuations. Imagine listening to a motivating mixtape through headphones, running for 30\nminutes, fully in the groove. Then you sneeze, stumble, momentarily lose the beat \u2014 but a few seconds later\nyou are back in sync with the music. After four or five hours in the blazing summer heat, your muscles begin to\ntire and your step starts to drift off the beat. The same phenomenon occurs \u2014 with far smaller deviations \u2014 in\nevery clock source.\nBeyond drift, there are low-frequency fluctuations in phase \u2014 phase noise \u2014 caused by environmental\ninfluences such as temperature variation, power supply instability, or mechanical stress. This low-frequency\n\"wobble\" below 10 Hz is called Clock Wander. High-frequency phase noise above 10 Hz is called Clock Jitter,\nand it comes in two distinct varieties. Matter is fundamentally never at rest; the purity and properties of\nsemiconductors vary in quality. This gives rise to Random Jitter, which follows an unpredictable Gaussian\ndistribution \u2014 almost as if matter itself were an overarching clock source, the fundamental noise floor of time.\nDeterministic Jitter, by contrast, is consistent and repeatable \u2014 the consequence of our own design decisions.\nElectronic circuits suffer from crosstalk, power supply ripple, electromagnetic interference, and impedance\nmismatches. Clock jitter is a \"tremor\" around the target frequency at which the oscillator is supposed to run.<\/p>\n\n\n\n<p><\/p>\n\n\n\n<p><strong>Synchronisation Accuracy<\/strong><br>Every digital transmission system requires a shared clock reference. The Clock Leader is the authoritative time\nreference for all Clock Followers, which lock to it using a PLL (Phase-Locked Loop) circuit that nudges their\ninternal oscillator faster or slower as required. How well a system achieves this is described by its\nsynchronisation accuracy. In Dante with PTPv1, the target synchronisation accuracy is 1 \u00b5s between a single\ntransmitter and receiver pair, and 2 \u00b5s in multi-receiver configurations. Under degraded network conditions, a\nguaranteed synchronisation accuracy of one sample length is maintained.<\/p>\n\n\n\n<p><strong>What Time Is It \u2014 Really?<\/strong><br>The most precise clock we know of is the atomic clock, which derives its time reference from the radiation\ntransitions of electrons in free atoms. Caesium, rubidium, hydrogen, and more recently strontium are the most\ncommon atoms used, with a drift of approximately one second per 300 million years. While this may seem like\nmore than enough precision to keep an appointment, it is in fact insufficient for the highly precise technology\nwe have built. Even an atomic clock drifts by 1 nanosecond after approximately 110 days.<br>If we want to synchronise to 1 ns precision globally \u2014 for example, to achieve 1-metre GPS positioning\naccuracy \u2014 we need a more elaborate approach. We therefore average the historical measurements of some\n400 atomic clocks at 60 institutions worldwide to form the International Atomic Time (TAI), from which the\nCoordinated Universal Time (UTC) is derived. This is, in essence, Leader Clock Number One. GPS satellites\ncarrying their own atomic clocks, synchronised to ground stations, form Leader Clock Number Two. These two\nsystems are not synchronised to each other; they run independently, typically diverging by no more than\napproximately 20 ns. UTC is not directly relevant to the rest of this discussion, but one fact is worth noting: due\nto the Earth's irregular rotation, leap seconds are periodically inserted to keep UTC aligned. GPS time, by\ncontrast, has been running continuously since 1980. GPS time therefore currently runs exactly 18 seconds\nahead of UTC. TAI had a 10-second head start over UTC at its launch in 1972, and a 19-second lead over GPS\ntime at the GPS epoch of 6 January 1980 at 00:00:00 \u2014 an offset that has remained constant since. TAI and GPS\nboth run continuously without leap seconds. As of May 2026, TAI leads UTC by 37 seconds (18 s + 19 s); this\nmust be taken into account when converting between PTP\/TAI and UTC.<\/p>\n\n\n\n<h4 class=\"wp-block-heading\" style=\"padding-top:var(--wp--preset--spacing--sm-24-r);padding-bottom:var(--wp--preset--spacing--xs-12-r)\"><strong>Reference: GPS Jitter<\/strong><\/h4>\n\n\n\n<p>The GPS system is an excellent source of high-precision, globally synchronised time information. The jitter level\ndepends heavily on the quality of the receiver: the receiver's internal oscillator must suppress the inherent GPS\njitter. Typical values range from a few nanoseconds to 50\u2013100 ns; at the higher end, the timing is effectively\nderived from the receiver's own oscillator and only disciplined by GPS.<\/p>\n\n\n\n<h4 class=\"wp-block-heading\" style=\"padding-top:var(--wp--preset--spacing--sm-24-r);padding-bottom:var(--wp--preset--spacing--xs-12-r)\"><strong>Reference: Wordclock-Jitter<\/strong><\/h4>\n\n\n\n<p>The datasheet of an industry-benchmark wordclock generator provides the following specifications:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Drift: \u00a0\u00a0 Clock frequency leader mode: \u00a0\u00a0\u00a0\u00a0\u00a0 44.1 or 48 kHz \u00b1 25 PPM, -5 +50 \u00b0C.<\/li>\n\n\n\n<li>Jitter:\u00a0\u00a0\u00a0 Intrinsic clock jitter:        \u00a0\u00a010Hz)<br><br><\/li>\n<\/ul>\n\n\n\n<p>GPS offers lower drift; the wordclock offers lower jitter. In broadcast environments, both techniques are\ntherefore combined.<\/p>\n\n\n\n<p><\/p>\n\n\n\n<h4 class=\"wp-block-heading\"><strong>Reference: Jitter Perception Threshold in Digital Audio Transmission<\/strong><\/h4>\n\n\n\n<p><\/p>\n\n\n\n<p>At the 105th AES Convention (26\u201329 September 1998, San Francisco), Eric Benjamin and Benjamin Gannon of\nDolby Laboratories presented their findings in AES Preprint 4826 (P-1) on the audibility of jitter in digital audio.\nAcross various listener groups and audio signals, hearing thresholds were found to range between 20 and 330\nns.<\/p>\n\n\n\n<p><br><\/p>\n\n\n\n<figure class=\"wp-block-table\"><table class=\"has-fixed-layout\"><tbody><tr><td><strong>Reference<\/strong><strong><\/strong><\/td><td><strong>Tolerance Window<\/strong><strong><\/strong><\/td><\/tr><tr><td>Waveguide (\u03bb\/4 condition) at 20 kHz<\/td><td>&lt; 12,5\u00b5s<\/td><\/tr><tr><td>Jitter perception threshold in digital audio<\/td><td>20-330ns<\/td><\/tr><\/tbody><\/table><figcaption class=\"wp-element-caption\"><em>Table 02: Approximate Intrinsic Jitter of Various Systems<\/em><br><br><br><\/figcaption><\/figure>\n\n\n\n<figure class=\"wp-block-table\"><table class=\"has-fixed-layout\"><tbody><tr><td><strong>Reference<\/strong><strong><\/strong><\/td><td><strong>Intrinsic jitter<\/strong><strong><\/strong><\/td><\/tr><tr><td>Atomic clock<\/td><td>1fs<\/td><\/tr><tr><td>Crystal oscillator<\/td><td>2ps<\/td><\/tr><tr><td>GPS as Grandmaster Clock<\/td><td>10-100ns<\/td><\/tr><tr><td>&nbsp;<\/td><td><\/td><\/tr><tr><td>Wordclock<\/td><td>0.5ps \u2013 5ns<\/td><\/tr><tr><td>Wordclock (extreme jitter)<\/td><td>50ns<\/td><\/tr><tr><td>&nbsp;<\/td><td>&nbsp;<\/td><\/tr><tr><td>AES3<\/td><td>\u00b1 270ns<\/td><\/tr><tr><td>DARS Grade 1 Clock<\/td><td>\u00b1 20ps<\/td><\/tr><tr><td>DARS Grade 2 Clock<\/td><td>\u00b1 520ps<\/td><\/tr><tr><td>MADI [125MHz]<\/td><td>80ns<\/td><\/tr><\/tbody><\/table><figcaption class=\"wp-element-caption\"><em>Table 02: Approximate Intrinsic Jitter of Various Systems<\/em><\/figcaption><\/figure>\n\n\n\n<p><\/p>\n\n\n\n<p><br><\/p>\n\n\n\n<h4 class=\"wp-block-heading\" style=\"padding-top:var(--wp--preset--spacing--sm-24-r);padding-bottom:var(--wp--preset--spacing--xs-12-r)\"><strong>Leader Clocks and Intrinsic Jitter in the Signal Chain<\/strong><\/h4>\n\n\n\n<p>The precision benchmark of 12.5 \u00b5s introduced at the outset refers to the mechanical construction of the line\narray system \u2014 the \"banana.\" Clock jitter of this magnitude is entirely unacceptable at the electronic level. The\nabsolute hearing threshold for jitter, across a range of signals and listeners, lies between 20 and 330 ns. An\nindustry-benchmark wordclock achieves an intrinsic jitter of  10 Hz). Peak values are typically\naround ten times higher \u2014 corresponding to the stumble in our running analogy<\/p>\n\n\n\n<p>Using such a clock source as Leader is only worthwhile if two conditions are met:<br><br><strong>1. The clock recovery in the Follower achieves a meaningful gain in precision.<\/strong><\/p>\n\n\n\n<p><strong>2. The clock distribution occurs without significant precision loss.<\/strong><br><br>It is a well-established fact that a precise clock is the single most critical quality parameter of any digital audio\ntransmission system.<\/p>\n\n\n\n<p>As recently as the early 2000s, leading digital mixing consoles could receive an audible upgrade from a high-\nquality external wordclock. However, in a large-scale blind test conducted in 2019, this could no longer be\nreproduced. Not a single participant \u2014 across all major consoles and experienced audio professionals \u2014 made\na statistically reliable identification. Technical evolution has made internal clock generation impressively\nprecise. Unfortunately, I am not aware of a single mixing console, system controller, or amplifier whose\ninternal intrinsic clock jitter is specified in a datasheet. The assumption is therefore that it lies somewhere in\nthe range of 20 ns to 1 ps. I welcome any better-documented information from the reader on this point.<\/p>\n\n\n\n<p><br><\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"683\" src=\"https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/01_-_Mischpult_Vergleich_in_Koeln_2019_-_sw-1024x683.jpg\" alt=\"\" class=\"wp-image-9618\" srcset=\"https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/01_-_Mischpult_Vergleich_in_Koeln_2019_-_sw-1024x683.jpg 1024w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/01_-_Mischpult_Vergleich_in_Koeln_2019_-_sw-300x200.jpg 300w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/01_-_Mischpult_Vergleich_in_Koeln_2019_-_sw-768x512.jpg 768w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/01_-_Mischpult_Vergleich_in_Koeln_2019_-_sw-1536x1024.jpg 1536w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/01_-_Mischpult_Vergleich_in_Koeln_2019_-_sw-2048x1366.jpg 2048w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/01_-_Mischpult_Vergleich_in_Koeln_2019_-_sw-18x12.jpg 18w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/01_-_Mischpult_Vergleich_in_Koeln_2019_-_sw-500x333.jpg 500w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/01_-_Mischpult_Vergleich_in_Koeln_2019_-_sw-800x533.jpg 800w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/01_-_Mischpult_Vergleich_in_Koeln_2019_-_sw-1280x854.jpg 1280w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/01_-_Mischpult_Vergleich_in_Koeln_2019_-_sw-1920x1280.jpg 1920w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption class=\"wp-element-caption\"><em>Image 01: Mixing Console Comparison, Cologne, 2019<\/em><\/figcaption><\/figure>\n\n\n\n<p><br><\/p>\n\n\n\n<h4 class=\"wp-block-heading\" style=\"padding-top:var(--wp--preset--spacing--sm-24-r);padding-bottom:var(--wp--preset--spacing--xs-12-r)\"><strong>Synchronisation in the IT Network<\/strong><\/h4>\n\n\n\n<p>Let us now approach the topic from the IT side. Media signals are packetised by the transmitter, distributed\nacross the network, and unpacked and reproduced by the receiver. Whether we are sending audio, video,\nlighting, or control data is initially irrelevant. There are competing solutions for how media data is packetised;\nthe packets themselves follow standardised formats.<\/p>\n\n\n\n<p>When a packet is being transmitted, the transfer must complete before the next packet can begin. Everything is\nsequential. 1 Gbit\/s links are faster than 100 Mbit\/s links, and 10 Gbit\/s links are faster still \u2014 but every\nindividual transfer is still handled one at a time. Packets must therefore be queued in buffers until their turn\ncomes. Quality of Service (QoS) markings allow higher-priority packets \u2014 such as synchronisation data \u2014 to be\ngiven preferential treatment by correctly configured switches. However, even the highest-priority packet\ncannot interrupt an ongoing transmission; it must wait for the current transfer to complete. This is known as\nBlocking Delay. Oversized packets such as Jumbo Frames extend this delay accordingly. Ethernet itself offers no\nguaranteed delivery times \u2014 it simply processes packets in order. The resulting variation in packet delivery\ntiming is formally termed PDV (Packet Delay Variation)<\/p>\n\n\n\n<h4 class=\"wp-block-heading\" style=\"padding-top:var(--wp--preset--spacing--sm-24-r);padding-bottom:var(--wp--preset--spacing--xs-12-r)\"><strong>Do Switches Make an Audible Difference?<\/strong><\/h4>\n\n\n\n<p>The short answer is: no. A functioning switch neither alters bits nor modifies frequency response. Nevertheless,\nthe question is valid, because network design determines the stability of the overall system.<\/p>\n\n\n\n<p><\/p>\n\n\n\n<p><strong>Thought experiment: File vs. Stream<\/strong><\/p>\n\n\n\n<p>To understand whether a switch affects audio quality, consider digital audio recording. Jitter introduced during\nrecording is \"baked in\" \u2014 neither re-clocking nor a switch can remove it afterwards. Whether a file resides on a\nlocal hard drive or is streamed from a server via a complex network path is irrelevant \u2014 as long as the PCM\ndata arrives bit-identically at the converter. The samples simply need to be played back in the correct order,\nclocked by the D\/A converter's timing reference.<\/p>\n\n\n\n<p><\/p>\n\n\n\n<p><strong>PTP and the Wall Clock: Nanosecond Time Reference in the Network<\/strong><br>Networks use the Precision Time Protocol (PTP) to establish a Wall Clock \u2014 a shared time reference with\nnanosecond resolution. PTP time started at 00:00:00 on 1 January 1970; its absolute reference corresponds to\nTAI. Seconds have been counted up since then using 48 bits \u2014 sufficient for approximately 8.9 million years \u2014\nwith a further 32 bits representing sub-nanosecond fractions. This is the fundamental mechanism since the first\nstandard, IEEE 1588-2002 (PTPv1).\nThe 2008 revision, PTPv2, added a 16-bit correction field, enabling PTP-aware switches to log the residence\ntime of PTP packets and support a more precise, peer-to-peer synchronisation mechanism. PTPv2 is not\nbackwards-compatible with PTPv1.\nFor even higher synchronisation precision, PTPv2.1 (2019) is backwards-compatible with PTPv2 and adds a\nfurther 16 bits to achieve resolution down to 15 femtoseconds. The CERN White Rabbit Project drove this\nrevision to meet the synchronisation requirements of quantum network infrastructure. For those who want the\nhighest possible precision, PTPv2.1-capable White Rabbit low-jitter switches are available \u2014 and what is good\nenough for automated high-frequency financial trading certainly cannot hurt in a high-end audio system.<\/p>\n\n\n\n<p><\/p>\n\n\n\n<p><strong>RTP and RTCP: Ordering the Chaos<\/strong><br>Audio samples are encapsulated in RTP (Real-time Transport Protocol) packets, each carrying sequence numbers\nand timestamps. RTCP (RTP Control Protocol) ensures that every packet can be precisely associated with the\nPTP Wall Clock time. Since Layer-2 Ethernet has no inherent interest in delivery order, these packets frequently\narrive \"shuffled\" at the receiver. A Jitter Buffer takes care of this: it holds incoming packets and plays them out\nin the correct sequence, clocked by the receiver's local oscillator \u2014 which is itself synchronised to the shared\nWall Clock via PTP.<\/p>\n\n\n\n<p><br><strong>The PLL as a Flywheel<\/strong><\/p>\n\n\n\n<p>The PLL as a Flywheel\nSince network packet jitter (PDV) is always significantly higher than acceptable media clock jitter, the PLL\n(Phase-Locked Loop) in the receiver is critical. Think of it as a heavy flywheel: its rotational inertia keeps it\nrunning smoothly despite disturbances. A well-designed PLL responds only very sluggishly to fluctuations (\"low\ncorner frequency\") and is not perturbed by every transient \"twitch\" in the network.<\/p>\n\n\n\n<p>A \"lightweight\" flywheel\nthat responded immediately to every network fluctuation would be a design failure.<\/p>\n\n\n\n<p>The switch therefore makes no audible difference through the data it carries, but it does influence the quality\nof synchronisation by determining the degree of \"calm\" (low PDV) with which the PLL in the receiver can\noperate. A stable PTP network is thus the foundation for a low-jitter media clock.<br><br><\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"459\" src=\"https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/02_-_Jitter-Buffer__PLL-1024x459.jpg\" alt=\"\" class=\"wp-image-9620\" srcset=\"https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/02_-_Jitter-Buffer__PLL-1024x459.jpg 1024w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/02_-_Jitter-Buffer__PLL-300x135.jpg 300w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/02_-_Jitter-Buffer__PLL-768x344.jpg 768w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/02_-_Jitter-Buffer__PLL-1536x689.jpg 1536w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/02_-_Jitter-Buffer__PLL-2048x918.jpg 2048w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/02_-_Jitter-Buffer__PLL-18x8.jpg 18w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/02_-_Jitter-Buffer__PLL-500x224.jpg 500w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/02_-_Jitter-Buffer__PLL-800x359.jpg 800w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/02_-_Jitter-Buffer__PLL-1280x574.jpg 1280w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/02_-_Jitter-Buffer__PLL-1920x861.jpg 1920w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption class=\"wp-element-caption\"><em>Image 02: Jitter Buffer &amp; PLL in the Receiver<\/em><\/figcaption><\/figure>\n\n\n\n<p><br><\/p>\n\n\n\n<h4 class=\"wp-block-heading\" style=\"padding-top:var(--wp--preset--spacing--sm-24-r);padding-bottom:var(--wp--preset--spacing--xs-12-r)\"><strong>IT System Architecture: A Comparison of Synchronisation Standards<\/strong><\/h4>\n\n\n\n<p>We now examine IT networks as transport media for various Audio-over-IP standards. Dante, developed by\nAudinate from 2006, targets a synchronisation accuracy of 1 \u00b5s between receivers (clock offset), with a\nguaranteed minimum of sample-accurate synchronisation. Given that PTPv2 was not defined until 2008, this is\na creditable achievement, enabled by hardware timestamping in the Dante nodes.<\/p>\n\n\n\n<p>A strict distinction must be drawn here: the synchronisation accuracy of Dante is 1 \u00b5s (in PTPv1 end-to-end\nmode). The physical packet jitter (PDV) on the network cable is often considerably higher. <\/p>\n\n\n\n<p>In PTPv1, switches\nhave no awareness of the protocol negotiated between the end devices (nodes) \u2014 they are \"Non-PTP-Aware.\"\nThis has the advantage of imposing no special requirements or costs on switch selection; even 100 Mbit\/s\nswitches and ports are not a disqualifying factor. The disadvantage, however, is that PDV in the network can\nreach up to 1 ms, which must be suppressed at the receiver through large jitter buffers and clock recovery.<br><br><\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"920\" height=\"1024\" src=\"https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/03_-_PTPv1_Dante-920x1024.jpg\" alt=\"\" class=\"wp-image-9621\" srcset=\"https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/03_-_PTPv1_Dante-920x1024.jpg 920w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/03_-_PTPv1_Dante-270x300.jpg 270w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/03_-_PTPv1_Dante-768x854.jpg 768w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/03_-_PTPv1_Dante-1381x1536.jpg 1381w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/03_-_PTPv1_Dante-1841x2048.jpg 1841w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/03_-_PTPv1_Dante-11x12.jpg 11w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/03_-_PTPv1_Dante-500x556.jpg 500w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/03_-_PTPv1_Dante-800x890.jpg 800w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/03_-_PTPv1_Dante-1280x1424.jpg 1280w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/03_-_PTPv1_Dante-1920x2136.jpg 1920w\" sizes=\"auto, (max-width: 920px) 100vw, 920px\" \/><figcaption class=\"wp-element-caption\"><em>Image 03: Network with Dante and PTPv1<\/em><\/figcaption><\/figure>\n\n\n\n<p><br><\/p>\n\n\n\n<p>Only PTPv2 with Transparent Clocks (TC) in the switches reduces synchronisation deviations to below 100\nnanoseconds, and with Boundary Clocks (BC) this can be optimised to below 50 nanoseconds.<br><br><\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"946\" height=\"1024\" src=\"https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/04_-_PTPv2TC-946x1024.jpg\" alt=\"\" class=\"wp-image-9622\" srcset=\"https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/04_-_PTPv2TC-946x1024.jpg 946w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/04_-_PTPv2TC-277x300.jpg 277w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/04_-_PTPv2TC-768x831.jpg 768w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/04_-_PTPv2TC-1419x1536.jpg 1419w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/04_-_PTPv2TC-1892x2048.jpg 1892w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/04_-_PTPv2TC-11x12.jpg 11w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/04_-_PTPv2TC-500x541.jpg 500w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/04_-_PTPv2TC-800x866.jpg 800w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/04_-_PTPv2TC-1280x1386.jpg 1280w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/04_-_PTPv2TC-1920x2078.jpg 1920w\" sizes=\"auto, (max-width: 946px) 100vw, 946px\" \/><figcaption class=\"wp-element-caption\"><em>Image 04: Network with AES67 and PTPv2 TC<\/em><\/figcaption><\/figure>\n\n\n\n<p><br><\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"1020\" src=\"https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/05_-_PTPv2BC-1024x1020.jpg\" alt=\"\" class=\"wp-image-9623\" srcset=\"https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/05_-_PTPv2BC-1024x1020.jpg 1024w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/05_-_PTPv2BC-300x300.jpg 300w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/05_-_PTPv2BC-150x150.jpg 150w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/05_-_PTPv2BC-768x765.jpg 768w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/05_-_PTPv2BC-1536x1530.jpg 1536w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/05_-_PTPv2BC-2048x2040.jpg 2048w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/05_-_PTPv2BC-12x12.jpg 12w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/05_-_PTPv2BC-500x498.jpg 500w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/05_-_PTPv2BC-800x797.jpg 800w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/05_-_PTPv2BC-1280x1275.jpg 1280w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/05_-_PTPv2BC-1920x1913.jpg 1920w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption class=\"wp-element-caption\"><em>Image 05: Network with AES67 and PTPv2 BC<\/em><\/figcaption><\/figure>\n\n\n\n<p><br><\/p>\n\n\n\n<p>An AVB\/TSN\/Milan network achieves even lower PDV values. However, the synchronisation accuracy of\nListeners to Talkers cannot be improved beyond what PTPv2 (BC) delivers for AES67, except under laboratory\nconditions.<br><br><\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"1008\" src=\"https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/06_-_gPTP-1024x1008.jpg\" alt=\"\" class=\"wp-image-9624\" srcset=\"https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/06_-_gPTP-1024x1008.jpg 1024w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/06_-_gPTP-300x295.jpg 300w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/06_-_gPTP-768x756.jpg 768w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/06_-_gPTP-1536x1512.jpg 1536w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/06_-_gPTP-2048x2016.jpg 2048w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/06_-_gPTP-12x12.jpg 12w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/06_-_gPTP-500x492.jpg 500w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/06_-_gPTP-800x788.jpg 800w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/06_-_gPTP-1280x1260.jpg 1280w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/06_-_gPTP-1920x1890.jpg 1920w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption class=\"wp-element-caption\"><em>Image 06: Network with Milan and gPTP<\/em><br><\/figcaption><\/figure>\n\n\n\n<p>It must be emphasised that all of the above refers to network synchronisation precision, not to media clock\njitter. The network's packet jitter (PDV) is suppressed by jitter buffers at the receiver inputs and by clock\nrecovery via the PLL. This is where the widely debated \"clock sound differences\" actually originate \u2014 not from\nthe network packets themselves. Minimising packet jitter in IT networks through good design remains a\nworthwhile goal, as it reduces the burden on the jitter buffers and the PLL.<\/p>\n\n\n\n<p><br><\/p>\n\n\n\n<h4 class=\"wp-block-heading\" style=\"padding-top:var(--wp--preset--spacing--sm-24-r);padding-bottom:var(--wp--preset--spacing--xs-12-r)\"><strong>The Mathematics of Summation: The +6 dB Paradox<\/strong><\/h4>\n\n\n\n<p>Let us briefly address something that borders on pedantry \u2014 but deliberately so. <br><br>We sum two coherent signals\nat 0 dBr each. What is the resulting level?&nbsp;<br><br>+6 dB? Incorrect.&nbsp;<\/p>\n\n\n\n<p>The exact value is +6,0206dB!\u00a0 [20 \u00d7 log \u2081\u2080(2) \u2248 6,0206 dB]<\/p>\n\n\n\n<p><br><\/p>\n\n\n\n<p>One might say, \"don't be so fussy.\" But today, pedantry serves a purpose, so let us turn this around. If we\nround down to exactly 6.0000 dB, we must mathematically accept a phase offset of 7.89\u00b0 at 20 kHz \u2014 which\ncorresponds to exactly 1.09 \u00b5s. In that time, sound in air travels approximately 0.37 mm. This corresponds to\nthe optimal synchronisation accuracy of Dante under ideal conditions \u2014 accuracy that can degrade, under\nadverse conditions such as high network load, Jumbo Frames, or 100 Mbit\/s trunks, to as much as one full\nsample length.<\/p>\n\n\n\n<h4 class=\"wp-block-heading\" style=\"padding-top:var(--wp--preset--spacing--sm-24-r);padding-bottom:var(--wp--preset--spacing--xs-12-r)\"><strong>Stress-Test<\/strong><\/h4>\n\n\n\n<p>Next, let us subject a Dante PTPv1-based line array system to deliberate network jitter stress. In a purpose-built\ntest system, it is possible to demonstrate a level error of 2 dB across the coverage area of a line array system\n(i.e. +4 dB instead of +6 dB summation). Assuming perfectly coherent signals at equal levels, this corresponds\nto a phase offset of 75\u00b0 at 20 kHz \u2014 equivalent to approximately 10 \u00b5s of clock offset, or almost exactly one\nsample period at 96 kHz. This is precisely within the maximum Dante system specification.<\/p>\n\n\n\n<p>Since clock recovery takes place in the receiver, and multiple receivers must be mutually synchronised, it makes\nsense to feed as many line array modules as possible from a single Audio-over-IP receiver with shared clock\nrecovery \u2014 analogous to the way a single mixing console handles the task. In a self-powered (active) line array\nmodule with an onboard Dante card, this maximum error under poor PTPv1 conditions is exactly what is at\nstake \u2014 an error that can be reduced to the precision values above by adopting PTPv2 with Boundary Clocks. A\nsystem amplifier with an Audio-over-IP input feeding, for example, three line array modules provides identical\nclocking to all three modules even under worst-case network conditions.&nbsp;<\/p>\n\n\n\n<h4 class=\"wp-block-heading\" style=\"padding-top:var(--wp--preset--spacing--sm-24-r);padding-bottom:var(--wp--preset--spacing--xs-12-r)\"><strong>The 1-Sample Trap | From Legacy Interfaces to Audio-over-IP<\/strong><\/h4>\n\n\n\n<p>Before system amplifiers were equipped with internal DSP processing, a central system controller handled all\nprocessing tasks for analogue amplifiers (amplifiers without DSP, regardless of topology \u2014 Class AB\/D\/H\/TD,\netc.). In such systems, there was only a single clock source, and the question of synchronising to a single Clock\nLeader was usually moot.<\/p>\n\n\n\n<p><br><\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"810\" src=\"https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/07_-_Analog_Wander-1024x810.jpg\" alt=\"\" class=\"wp-image-9625\" srcset=\"https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/07_-_Analog_Wander-1024x810.jpg 1024w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/07_-_Analog_Wander-300x237.jpg 300w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/07_-_Analog_Wander-768x608.jpg 768w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/07_-_Analog_Wander-1536x1216.jpg 1536w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/07_-_Analog_Wander-2048x1621.jpg 2048w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/07_-_Analog_Wander-15x12.jpg 15w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/07_-_Analog_Wander-500x396.jpg 500w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/07_-_Analog_Wander-800x633.jpg 800w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/07_-_Analog_Wander-1280x1013.jpg 1280w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/07_-_Analog_Wander-1920x1520.jpg 1920w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption class=\"wp-element-caption\"><em>Image 07: Analogue Wander<\/em><\/figcaption><\/figure>\n\n\n\n<p><br>The next generation of system amplifiers was equipped with DSPs and could assume the processing role of the\ncentral controller. What happens when such a system is driven with analogue input signals?<\/p>\n\n\n\n<p><br><\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"870\" src=\"https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/08_-_Analog_Wander_DSP-Amp_-_1-Sample_Trap-1024x870.jpg\" alt=\"\" class=\"wp-image-9626\" srcset=\"https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/08_-_Analog_Wander_DSP-Amp_-_1-Sample_Trap-1024x870.jpg 1024w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/08_-_Analog_Wander_DSP-Amp_-_1-Sample_Trap-300x255.jpg 300w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/08_-_Analog_Wander_DSP-Amp_-_1-Sample_Trap-768x652.jpg 768w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/08_-_Analog_Wander_DSP-Amp_-_1-Sample_Trap-1536x1304.jpg 1536w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/08_-_Analog_Wander_DSP-Amp_-_1-Sample_Trap-2048x1739.jpg 2048w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/08_-_Analog_Wander_DSP-Amp_-_1-Sample_Trap-14x12.jpg 14w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/08_-_Analog_Wander_DSP-Amp_-_1-Sample_Trap-500x425.jpg 500w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/08_-_Analog_Wander_DSP-Amp_-_1-Sample_Trap-800x679.jpg 800w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/08_-_Analog_Wander_DSP-Amp_-_1-Sample_Trap-1280x1087.jpg 1280w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/08_-_Analog_Wander_DSP-Amp_-_1-Sample_Trap-1920x1631.jpg 1920w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption class=\"wp-element-caption\"><em>Image 08: Analogue Wander DSP-Amp \u2014 1-Sample Trap<\/em><\/figcaption><\/figure>\n\n\n\n<p><br><\/p>\n\n\n\n<p>Each amplifier has a free-running clock. Assuming internal processing at 96 kHz and a drift of \u00b110 ppm against a\nperfect reference: Amplifier A's oscillator runs at 95,999.04 Hz, Amplifier B's at 96,000.96 Hz. After 1.04\nseconds, the two amplifiers drift apart by exactly one sample (10.4 \u00b5s) \u2014 if one oscillator is perfect and the\nother carries maximum drift. In the worst case, where both oscillators drift in opposite directions, this interval\nhalves accordingly. After approximately 28 hours, the total drift reaches one second \u2014 but there is no need for\nconcern: the signal does not actually arrive one second later at one output than the other. In this real-time\nsystem, there is no absolute time reference. The maximum error is always bounded to one sample length (10.4\n\u00b5s at 96 kHz); the \"LFO rate\" at which the error wanders within this window depends on oscillator precision.<\/p>\n\n\n\n<p>Since the period of a 20 kHz signal is only 50 \u00b5s, a one-sample offset already produces a phase shift of up to 75\u00b0\nat 20 kHz. This error is exactly equivalent to the Dante PTPv1 worst-case scenario and produces the measured 2\ndB level deviation at high frequencies. The system, protected by the analogue \"guardrail,\" never reaches full\ncancellation (180\u00b0 at 25 \u00b5s), but it permanently oscillates within a range that destabilises acoustic coupling.\nFrom this perspective, driving as many array modules as possible from a single amplifier is preferable \u2014 though\nthis must be weighed against the power headroom and beam-steering requirements that necessitate individual\ndrive per module.<\/p>\n\n\n\n<p>Analogue signal distribution protects against the total timing chaos of unsynchronised networks, but leaves\nsystems trapped in the 1-Sample Trap. Only modern standards such as Milan or PTPv2 break this constraint,\nsynchronising the converters so precisely that phase errors at 20 kHz become physically irrelevant.\nAn instructive comparison is the digital classic AES3. The specification AES11-2009 (r2014) permits an input\ntolerance (jitter mask) of approximately 2.6% = \u00b1270 ns (total jitter window of 540 ns) of the sample interval,\nequivalent to approximately 0.5 \u00b5s at 96 kHz. Summing our two coherent signals again yields +6.01633 dB\ninstead of +6.0206 dB \u2014 a phase offset of 3.59\u00b0 at 20 kHz. This is why the +6 dB pedantry was necessary.\nThe internal PLL of the amplifiers filters this jitter and enables phase-locked playback. This value is the\ntechnological benchmark: a system using Milan or PTPv2 (BC) today delivers a clock signal that is already 5 to\n10 times more precise at the input than the absolute limit of the classic AES3 interface.<\/p>\n\n\n\n<p><br><\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"870\" src=\"https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/09_-_AES_Wander_DSP-Amp-1024x870.jpg\" alt=\"\" class=\"wp-image-9627\" srcset=\"https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/09_-_AES_Wander_DSP-Amp-1024x870.jpg 1024w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/09_-_AES_Wander_DSP-Amp-300x255.jpg 300w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/09_-_AES_Wander_DSP-Amp-768x653.jpg 768w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/09_-_AES_Wander_DSP-Amp-1536x1305.jpg 1536w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/09_-_AES_Wander_DSP-Amp-2048x1740.jpg 2048w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/09_-_AES_Wander_DSP-Amp-14x12.jpg 14w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/09_-_AES_Wander_DSP-Amp-500x425.jpg 500w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/09_-_AES_Wander_DSP-Amp-800x680.jpg 800w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/09_-_AES_Wander_DSP-Amp-1280x1088.jpg 1280w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/09_-_AES_Wander_DSP-Amp-1920x1631.jpg 1920w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption class=\"wp-element-caption\"><em>Image 09: AES3 Wander DSP-Amp<\/em><\/figcaption><\/figure>\n\n\n\n<p><br><\/p>\n\n\n\n<p>Next, we equip active self-powered line array modules with Audio-over-IP inputs. Synchronisation accuracy\nnow depends on the AoIP standard in use, as well as the operating conditions \u2014 essentially: stressed or\nunstressed network?<\/p>\n\n\n\n<p><br><\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"757\" src=\"https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/10_-_AoIP-Wander_Line-Array-1024x757.jpg\" alt=\"\" class=\"wp-image-9628\" srcset=\"https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/10_-_AoIP-Wander_Line-Array-1024x757.jpg 1024w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/10_-_AoIP-Wander_Line-Array-300x222.jpg 300w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/10_-_AoIP-Wander_Line-Array-768x568.jpg 768w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/10_-_AoIP-Wander_Line-Array-1536x1135.jpg 1536w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/10_-_AoIP-Wander_Line-Array-2048x1514.jpg 2048w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/10_-_AoIP-Wander_Line-Array-16x12.jpg 16w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/10_-_AoIP-Wander_Line-Array-500x370.jpg 500w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/10_-_AoIP-Wander_Line-Array-800x591.jpg 800w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/10_-_AoIP-Wander_Line-Array-1280x946.jpg 1280w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/10_-_AoIP-Wander_Line-Array-1920x1419.jpg 1920w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption class=\"wp-element-caption\"><em>Image 10: AoIP Wander Line Array<\/em><\/figcaption><\/figure>\n\n\n\n<p><br><\/p>\n\n\n\n<p>A further topology is to integrate AoIP inputs into the system amplifiers. In this case, phase errors and the\nresulting level modulation appear only at the module boundaries driven by the next amplifier.<\/p>\n\n\n\n<p><br><\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"738\" src=\"https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/11_-_AoIP_Wander_Line-Array_with_DSP-Amp-1024x738.jpg\" alt=\"\" class=\"wp-image-9629\" srcset=\"https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/11_-_AoIP_Wander_Line-Array_with_DSP-Amp-1024x738.jpg 1024w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/11_-_AoIP_Wander_Line-Array_with_DSP-Amp-300x216.jpg 300w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/11_-_AoIP_Wander_Line-Array_with_DSP-Amp-768x554.jpg 768w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/11_-_AoIP_Wander_Line-Array_with_DSP-Amp-1536x1107.jpg 1536w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/11_-_AoIP_Wander_Line-Array_with_DSP-Amp-2048x1476.jpg 2048w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/11_-_AoIP_Wander_Line-Array_with_DSP-Amp-18x12.jpg 18w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/11_-_AoIP_Wander_Line-Array_with_DSP-Amp-500x360.jpg 500w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/11_-_AoIP_Wander_Line-Array_with_DSP-Amp-800x577.jpg 800w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/11_-_AoIP_Wander_Line-Array_with_DSP-Amp-1280x923.jpg 1280w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/11_-_AoIP_Wander_Line-Array_with_DSP-Amp-1920x1384.jpg 1920w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption class=\"wp-element-caption\"><em>Image 11: AoIP Wander Line Array with DSP Amp<\/em><\/figcaption><\/figure>\n\n\n\n<p><br><\/p>\n\n\n\n<h4 class=\"wp-block-heading\"><strong>Summary Table: PDV and Synchronisation Accuracy Across Audio System Scenarios<\/strong><\/h4>\n\n\n\n<p><br><\/p>\n\n\n\n<figure class=\"wp-block-table\"><table class=\"has-fixed-layout\"><tbody><tr><td><strong>System Scenario<\/strong><strong><\/strong><\/td><td><strong>Jitter \/ PDV (Input)<\/strong><strong><\/strong><\/td><td><strong>Sync Accuracy (Node)<\/strong><strong><\/strong><\/td><td><strong>Total level<br>@ 20 kHz<\/strong><strong><\/strong><\/td><td><strong>Acoustic Behaviour<\/strong><strong><\/strong><\/td><\/tr><tr><td>AES3<\/td><td>~500 ns (0.5 \u00b5s)<\/td><td>&lt; 20 ns (PLL)<\/td><td>6,02 dB<\/td><td>Phase-locked (reference)<\/td><\/tr><tr><td>AVB\/TSN Milan (gPTP)<\/td><td>&lt; 50 ns<\/td><td>~50 ns<\/td><td>6,02 dB<\/td><td>Absolutely coherent wavefront<\/td><\/tr><tr><td>AES67 (BC Mode)<\/td><td>&lt; 100 ns<\/td><td>~50 ns<\/td><td>6,02 dB<\/td><td>Reference class (phase-locked)<\/td><\/tr><tr><td>AES67 (TC Mode)<\/td><td>&lt; 1,000 ns (1 \u00b5s)<\/td><td>~100 ns<\/td><td>6,02 dB<\/td><td>Very stable<\/td><\/tr><tr><td>Dante (Best Case)<\/td><td>1,000,000 ns (1 ms)<\/td><td>~1,000 ns (1 \u00b5s)<\/td><td>6.00 dB<\/td><td>Industry standard<\/td><\/tr><tr><td>Dante (Worst Case)<\/td><td>1,000,000 ns (1 ms)<\/td><td>~10,420 ns (1 sample)<\/td><td>~4.01 dB<\/td><td>HF level reduction (static)<\/td><\/tr><tr><td>Analog-In (DSP)<\/td><td>n.a. (copper cable)<\/td><td>~10,420 ns (1 sample)<\/td><td>6,02 \u2013 4,01 dB<\/td><td>HF level modulation (dynamic)<\/td><\/tr><\/tbody><\/table><figcaption class=\"wp-element-caption\"><em>Table 03: Overview of various Audio-over-IP networks and their typical network jitter (PDV), the achievable synchronisation precision of the\nnodes, and the resulting phase error expressed as summation level at 20 kHz.<\/em><\/figcaption><\/figure>\n\n\n\n<p><br><\/p>\n\n\n\n<h4 class=\"wp-block-heading\" style=\"padding-top:var(--wp--preset--spacing--sm-24-r);padding-bottom:var(--wp--preset--spacing--xs-12-r)\"><strong>The ASRC Trap<\/strong><\/h4>\n\n\n\n<p>In practice, differing sample rates must often be reconciled within the same system. This is where Sample Rate\nConverters (SRC) come into play. Synchronous SRCs pass the drift through rigidly; asynchronous converters\n(ASRCs) interpolate it continuously. Since they form a clock domain boundary, they must be positioned strictly\nat the edges of the system. If they are deployed multiple times in series within a line array segment, they\ninduce uncontrollable latency offsets that simply destroy the acoustic coherence at high frequencies \u2014 the\nresult of painstaking engineering effort. This is precisely why such configurations are avoided in practice: every\narray segment must be fed synchronously from a single clock domain, and the number of links is kept to a\nminimum to prevent interface jitter accumulation.\n\nSystem amplifiers that include SRCs in their AES3 inputs \u2014 which cannot be disabled via menu settings and are\npoorly documented in terms of their type (SRC vs. ASRC) \u2014 introduce additional error sources that degrade\nsynchronisation accuracy.<\/p>\n\n\n\n<p>Although modern ASRCs exhibit deterministic latency, they remain a clock domain boundary. Since each\nmodule in the array must independently estimate and regulate the ratio between its input and output clock,\neven tiny deviations in the tracking algorithms and filter group delays can lead to phase inconsistencies. In a\nsystem that depends on microsecond-level precision, this distributed clock recovery is an unnecessary risk. A\nsystem design that cascades ASRCs within media signal clusters is therefore the wrong approach. Sequential\ninterpolation stages, each with their own filter artefacts and jitter transfer functions, smear the signal in time.\nThink of each ASRC as an independent \"decision-maker\" \u2014 but a line array system requires a single, system-\nwide \"truth.\"<\/p>\n\n\n\n<p><br><\/p>\n\n\n\n<h4 class=\"wp-block-heading\" style=\"padding-top:var(--wp--preset--spacing--sm-24-r);padding-bottom:var(--wp--preset--spacing--xs-12-r)\"><strong>Summary: <\/strong><\/h4>\n\n\n\n<h4 class=\"wp-block-heading\"><strong>Criteria for a Phase-Coherent Audio-over-IP System Design<\/strong><\/h4>\n\n\n\n<p><br><\/p>\n\n\n\n<p><\/p>\n\n\n\n<p>Compared to PTPv1 with hardware timestamping in Dante modules (&lt; 1 \u00b5s synchronisation accuracy), PTPv2\noffers up to 10\u00d7 greater precision with Transparent Clocks (&lt; 100 ns) and up to 20\u00d7 greater precision with\nBoundary Clocks (&lt; 50 ns).\nTo restate this clearly: Network Packet Jitter (PDV) \u2260 Media Clock Jitter. Audio quality is determined by clock\nrecovery in the receiver \u2014 this is the decisive parameter.\nIn 2026, we do not need &quot;miracle switches.&quot; We need clean system design: a precise Clock Leader, star-\ntopology distribution, and the consistent elimination of free-running clocks or asynchronous sample rate\nconverters within any line array segment. With these fundamentals in place, Audio-over-IP offers precision that\nis fully on a par with the mechanical construction of modern line arrays, and renders the drawbacks of\ninterface-jitter-prone, daisy-chained AES3 wiring obsolete.<strong>,<\/strong> AES3, Milan, AES67 (TC or BC), and Dante under best-case conditions are all equally capable of delivering\nprecise audio signals to line array loudspeaker systems. Only Dante with PTPv1 under worst-case conditions\nfalls into the same 1-Sample Trap as free-running DSP amplifiers driven by analogue inputs. The key distinction\nis that in the analogue case, the 75\u00b0 phase error (2 dB level deviation) modulates dynamically and relatively\nquickly between the ideal +6 dB and the degraded +4 dB \u2014 whereas the error in Dante worst-case is\ncomparatively static, and only arises when the receive cards are integrated directly into the line array modules\nthemselves.\nWhoever wants to preserve the precision of a modern waveguide without squandering it at the electronic level\nmust make converter synchronisation the highest priority.<\/p>\n\n\n\n<p><br><\/p>\n\n\n\n<h4 class=\"wp-block-heading\" style=\"padding-top:var(--wp--preset--spacing--sm-24-r);padding-bottom:var(--wp--preset--spacing--xs-12-r)\"><strong>Calculator: <\/strong><br>PTP time, drift, jitter, sync, signal runtime in cables<\/h4>\n\n\n\n<p>Of course, the statements made here must also be mathematically plausible and comprehensible. Here you will find a calculator with which you can perform the following calculations:<br><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Convert UTC time to PTP time<\/li>\n\n\n\n<li>Convert PTP time to UTC time<\/li>\n\n\n\n<li>Calculate signal runtime over cable length<\/li>\n\n\n\n<li>Calculate clock drift, drift up to 1 sample and drift up to 1s difference, phase difference of clock drift at selectable frequency<\/li>\n\n\n\n<li>Calculate jitter in the nano- and microsecond range<\/li>\n\n\n\n<li>Calculate synchronization accuracy<\/li>\n\n\n\n<li>Conversion: Enter frequency and phase difference and calculate latency offset and sum level<\/li>\n\n\n\n<li>Conversion: Input total level of two coherent signals per 0dBr and calculate phase difference, as well as latency and sample offset<br><\/li>\n<\/ul>\n\n\n\n<figure class=\"wp-block-image size-full\"><a href=\"https:\/\/docs.google.com\/spreadsheets\/d\/1_80wzgFiI2MtA3tw-4PkpYmVeewsp1sWvoNWF3Z9Pfg\/edit?usp=sharing\" target=\"_blank\" rel=\" noreferrer noopener\"><img loading=\"lazy\" decoding=\"async\" width=\"264\" height=\"264\" src=\"https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/Bodo-Felusch-QR-Code-Calculator-PTP-Time-Jitter.png\" alt=\"\" class=\"wp-image-9560\" srcset=\"https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/Bodo-Felusch-QR-Code-Calculator-PTP-Time-Jitter.png 264w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/Bodo-Felusch-QR-Code-Calculator-PTP-Time-Jitter-150x150.png 150w, https:\/\/felusch.de\/wp-content\/uploads\/2026\/05\/Bodo-Felusch-QR-Code-Calculator-PTP-Time-Jitter-12x12.png 12w\" sizes=\"auto, (max-width: 264px) 100vw, 264px\" \/><\/a><\/figure>\n\n\n\n<p><br><\/p>\n\n\n<section class='__wpdm_gb_section __wpdm_gb_package'><div class='w3eden'><!-- WPDM Link Template: Default Template -->\n\n<div class=\"felusch-download-card\">\n    <div class=\"felusch-download-card-body\">\n        <div class=\"felusch-download-card-media\">\n            <div class=\"felusch-download-card-icon\"><img decoding=\"async\" class=\"wpdm_icon\" alt=\"icon\"   src=\"https:\/\/cdn0.iconfinder.com\/data\/icons\/logos-microsoft-office-365\/128\/Microsoft_Office-02-512.png\" \/><\/div>\n            <div class=\"felusch-download-card-title-and-meta\">\n                <h3 class=\"felusch-download-card-title\">Excel Calculator - PTP time - Jitter - Signal-Propagation (EN)<\/h3>\n                <div class=\"felusch-download-card-meta\">\n                    <div class=\"felusch-download-card-meta-entry\">\n                        <div style=\"display: flex; align-items: center;\">\n                            <svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"22\" height=\"22\" fill=\"#7C7C7C\" viewbox=\"0 0 256 256\">\n                                <path d=\"M210.83,69.17l-40-40A4,4,0,0,0,168,28H88A12,12,0,0,0,76,40V60H56A12,12,0,0,0,44,72V216a12,12,0,0,0,12,12H168a12,12,0,0,0,12-12V196h20a12,12,0,0,0,12-12V72A4,4,0,0,0,210.83,69.17ZM172,216a4,4,0,0,1-4,4H56a4,4,0,0,1-4-4V72a4,4,0,0,1,4-4h78.34L172,105.66Zm32-32a4,4,0,0,1-4,4H180V104a4,4,0,0,0-1.17-2.83l-40-40A4,4,0,0,0,136,60H84V40a4,4,0,0,1,4-4h78.34L204,73.66Zm-64-32a4,4,0,0,1-4,4H88a4,4,0,0,1,0-8h48A4,4,0,0,1,140,152Zm0,32a4,4,0,0,1-4,4H88a4,4,0,0,1,0-8h48A4,4,0,0,1,140,184Z\"><\/path>\n                            <\/svg>\n\n                        <\/div>\n                        1 file(s)\n                    <\/div>\n\n                    <div class=\"felusch-download-card-meta-entry\">\n                        <div style=\"display: flex; align-items: center;\">\n                            <svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"22\" height=\"22\" fill=\"#7C7C7C\" viewbox=\"0 0 256 256\">\n                                <path d=\"M236,136v64a12,12,0,0,1-12,12H32a12,12,0,0,1-12-12V136a12,12,0,0,1,12-12H72a4,4,0,0,1,0,8H32a4,4,0,0,0-4,4v64a4,4,0,0,0,4,4H224a4,4,0,0,0,4-4V136a4,4,0,0,0-4-4H184a4,4,0,0,1,0-8h40A12,12,0,0,1,236,136Zm-110.83-5.17a4,4,0,0,0,5.66,0l48-48a4,4,0,1,0-5.66-5.66L132,118.34V24a4,4,0,0,0-8,0v94.34L82.83,77.17a4,4,0,0,0-5.66,5.66ZM196,168a8,8,0,1,0-8,8A8,8,0,0,0,196,168Z\"><\/path>\n                            <\/svg>\n                        <\/div> 90KB\n                    <\/div>\n\n                <\/div>\n            <\/div>\n        <\/div>\n        <div class=\"felusch-download-card-link\">\n            <form method=\"post\" action=\"\" name=\"cart_form\" class=\"wpdm_cart_form\" id=\"wpdm_cart_form_9592\" data-etm-original-action=\"\">\n                    <input type=\"hidden\" name=\"addtocart\" value=\"9592\">    <button class=\"btn btn-primary  btn-addtocart btn-addtocart-9592\"\n            data-cart-redirect=\"on\"\n            type=\"submit\" >Buy with Paypal <span\n                class=\"price-9592 label label-price\">5,99\u20ac<\/span><\/button>\n    <input type=\"hidden\" name=\"etm-form-language\" value=\"en\"\/><\/form>\n        <\/div>\n\n    <\/div>\n<\/div><\/div><\/section>\n\n\n<div style=\"height:100px\" aria-hidden=\"true\" class=\"wp-block-spacer\"><\/div>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>Want to go deeper?<\/strong><\/h2>\n\n\n\n<p>Precision in the network is not a coincidence \u2014 it is the result of understanding your system. Anyone who knows why a line array loses coherence at 20 kHz can prevent it.<\/p>\n\n\n\n<p><strong>IT For AVs\u00ae \u2013 Networking for Event Technicians<\/strong> teaches the IT fundamentals that live event technicians actually need \u2014 in three days. And for those who want to go further: Mastering Event IT is coming as an additional module. One day, straight to the point: media networks and their IT requirements, PTP and synchronisation, routing fundamentals. Feeding internet into a venue and distributing it to specific disciplines \u2014 even on client networks where you never get near the router. Connecting a media server in the video VLAN with the lighting desk in the lighting VLAN. Thinking across disciplines, working across disciplines. <strong>IT For AVs\u00ae<\/strong> is currently taught in German. An English edition is in development.<\/p>\n\n\n\n<p><strong>if you want to be first to know when it launches, sign up below.<\/strong> <strong>No spam, no tricks. Just a signal when it matters.<\/strong><\/p>\n\n\n\n<p><br><\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>\u2192 I'm in<\/strong>:<\/h2>\n\n\n\n<div class=\"wp-block-ermisch-block-flex-block flex-block has-ermisch-dimensions has-ermisch-spacing has-ermisch-borders has-ermisch-flexbox has-bg-2-background-color has-background is-layout-flow wp-block-ermisch-block-flex-block-is-layout-flow\" data-style-id=\"flex-1bf9ce61\" id=\"waitlist\">\n<div class=\"wp-block-ermisch-block-flex-block flex-block has-ermisch-dimensions has-ermisch-spacing has-ermisch-borders has-ermisch-flexbox is-layout-flow wp-block-ermisch-block-flex-block-is-layout-flow\" data-style-id=\"flex-b25d736e\">\n<h3 class=\"wp-block-heading\">Waiting list<\/h3>\n<\/div>\n\n\n\n<div class=\"wp-block-ermisch-block-flex-block flex-block has-ermisch-dimensions has-ermisch-spacing has-ermisch-borders has-ermisch-flexbox is-layout-flow wp-block-ermisch-block-flex-block-is-layout-flow\" data-style-id=\"flex-4c1461ae\">\n<p>Sign up for my waiting list and let yourself be informed by e-mail if appointments are still available at short notice or new ones are set. <\/p>\n\n\n\n<div class=\"wp-block-ermisch-block-flex-block flex-block has-ermisch-dimensions has-ermisch-spacing has-ermisch-borders has-ermisch-flexbox is-layout-flow wp-block-ermisch-block-flex-block-is-layout-flow\" data-style-id=\"flex-33647b72\"><div class=\"tnp tnp-subscription felusch-waitlist\">\n<form method=\"post\" action=\"https:\/\/felusch.de\/wp-admin\/admin-ajax.php?action=tnp&amp;na=s\"><div class=\"tnp-field tnp-field-company\" \n    >\n<label for=\"tnp-company\">Company name\n<input class=\"tnp-company\" type=\"text\" name=\"company\" id=\"tnp-company\" autocomplete=\"off\" aria-hidden=\"true\" tabindex=\"-1\" value=\"\"><\/label>\n<\/div>\n<input type=\"hidden\" name=\"nlang\" value=\"\">\n<div class=\"tnp-field tnp-field-firstname\"><label for=\"tnp-1\">Name:<\/label>\n<input class=\"tnp-name\" type=\"text\" name=\"nn\" id=\"tnp-1\" value=\"\" placeholder=\"Max Mustermann\" required><\/div>\n<div class=\"tnp-field tnp-field-email\"><label for=\"tnp-2\">E-mail:<\/label>\n<input class=\"tnp-email\" type=\"email\" name=\"ne\" id=\"tnp-2\" value=\"\" placeholder=\"you@example.com\" required><\/div>\n<div class=\"tnp-field tnp-lists\"><label for=\"tnp-3\">Language:<\/label>\n<select class=\"tnp-lists\" name=\"nl[]\" required><option value=\"1\">German<\/option><option value=\"2\">English<\/option><\/select><\/div><div class=\"tnp-field tnp-privacy-field\"><label><input type=\"checkbox\" name=\"ny\" required class=\"tnp-privacy\"> <a target=\"_blank\" href=\"https:\/\/felusch.de\/en\/datenschutzerklaerung\/\">I accept the privacy policy.<\/a><\/label><\/div><div class=\"tnp-field tnp-field-button\" style=\"text-align: left\"><input class=\"tnp-submit\" type=\"submit\" value=\"Send me dates!\" style=\"\">\n<\/div>\n<\/form>\n<\/div>\n\n<\/div>\n<\/div>\n<\/div>\n\n\n\n<div style=\"height:100px\" aria-hidden=\"true\" class=\"wp-block-spacer\"><\/div>\n\n\n\n<h2 class=\"wp-block-heading\">List of sources<\/h2>\n\n\n\n<p><strong>Perception &amp; Psychoacoustics<\/strong><\/p>\n\n\n\n<p><strong>[1]&nbsp; <\/strong>E. Benjamin, B. Gannon (Dolby Laboratories): <em>\"Audibility of Jitter in Digital Audio Transmission\"<\/em>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; AES Preprint 4826, 105th AES Convention, San Francisco, September 1998&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <a href=\"https:\/\/www.aes.org\/e-lib\/browse.cfm?elib=8174\">https:\/\/www.aes.org\/e-lib\/browse.cfm?elib=8174<\/a><\/p>\n\n\n\n<p><strong>[2]&nbsp; <\/strong>B. C. J. Moore: <em>An Introduction to the Psychology of Hearing<\/em>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 6th Edition, Brill Academic Publishers, 2012. ISBN 978-9004252424 (Auditory threshold and temporal resolution)<\/p>\n\n\n\n<p><strong>Clock &amp; Synchronization standards<\/strong><\/p>\n\n\n\n<p><strong>[3]&nbsp; <\/strong>IEEE: <em>\u2018IEEE Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems \u2013 PTPv1\u2019<\/em>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; IEEE Std 1588-2002&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <a href=\"https:\/\/doi.org\/10.1109\/IEEESTD.2002.94144\">https:\/\/doi.org\/10.1109\/IEEESTD.2002.94144<\/a><\/p>\n\n\n\n<p><strong>[4]&nbsp; <\/strong>IEEE: <em>\u2018IEEE Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems \u2013 PTPv2\u2019<\/em>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; IEEE Std 1588-2008&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <a href=\"https:\/\/doi.org\/10.1109\/IEEESTD.2008.4579760\">https:\/\/doi.org\/10.1109\/IEEESTD.2008.4579760<\/a><\/p>\n\n\n\n<p><strong>[5]&nbsp; <\/strong>IEEE: <em>\u2018IEEE Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems \u2013 PTPv2.1\u2019<\/em>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; IEEE Std 1588-2019&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <a href=\"https:\/\/doi.org\/10.1109\/IEEESTD.2020.9120376\">https:\/\/doi.org\/10.1109\/IEEESTD.2020.9120376<\/a><\/p>\n\n\n\n<p><strong>[6]&nbsp; <\/strong>BIPM \/ IERS: <em>Coordinated Universal Time (UTC) and International Atomic Time (TAI)<\/em>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Bureau International des Poids et Mesures&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <a href=\"https:\/\/www.bipm.org\/en\/time-ftp\/tai\">https:\/\/www.bipm.org\/en\/time-ftp\/tai<\/a><\/p>\n\n\n\n<p><strong>[7]&nbsp; <\/strong>U.S. Space Force: <em>\u2018IS-GPS-200: NAVSTAR GPS Space Segment\/Navigation User Segment Interfaces\u2019<\/em>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; GPS Interface Specification, current revision&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <a href=\"https:\/\/www.gps.gov\/technical\/icwg\/\">https:\/\/www.gps.gov\/technical\/icwg\/<\/a><\/p>\n\n\n\n<p><strong>Audio Interface &amp; Digital Audio Standards<\/strong><\/p>\n\n\n\n<p><strong>[8]&nbsp; <\/strong>AES: <em>\u2018AES standard for digital audio \u2013 Serial transmission format for two-channel linearly represented digital audio data\u2019<\/em>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; AES3-2009, Audio Engineering Society&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <a href=\"https:\/\/www.aes.org\/publications\/standards\/search.cfm?docID=2\">https:\/\/www.aes.org\/publications\/standards\/search.cfm?docID=2<\/a><\/p>\n\n\n\n<p><strong>[9]&nbsp; <\/strong>AES: <em>\u201cAES recommended practice for digital audio \u2013 Synchronization of digital audio equipment in studio operations\u201d<\/em>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; AES11-2009 (r2014), Audio Engineering Society&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <a href=\"https:\/\/www.aes.org\/publications\/standards\/search.cfm?docID=17\">https:\/\/www.aes.org\/publications\/standards\/search.cfm?docID=17<\/a><\/p>\n\n\n\n<p><strong>[10]&nbsp; <\/strong>AES: <em>AES standard for audio applications of networks \u2013 High-performance streaming audio-over-IP interoperability<\/em>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; AES67-2018, Audio Engineering Society&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <a href=\"https:\/\/www.aes.org\/publications\/standards\/search.cfm?docID=96\">https:\/\/www.aes.org\/publications\/standards\/search.cfm?docID=96<\/a><\/p>\n\n\n\n<p><strong>AVB \/ TSN \/ Milan<\/strong><\/p>\n\n\n\n<p><strong>[11]&nbsp; <\/strong>IEEE: <em>IEEE Standard for Local and Metropolitan Area Networks \u2013 Timing and Synchronization for Time-Sensitive Applications (gPTP)<\/em>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; IEEE Std 802.1AS-2020&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <a href=\"https:\/\/doi.org\/10.1109\/IEEESTD.2020.9121845\">https:\/\/doi.org\/10.1109\/IEEESTD.2020.9121845<\/a><\/p>\n\n\n\n<p><strong>[12]&nbsp; <\/strong>IEEE: <em>\u2018IEEE Standard for Local and Metropolitan Area Networks \u2013 Bridges and Bridged Networks (includes AVB\/TSN)\u2019<\/em>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; IEEE Std 802.1Q-2022&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <a href=\"https:\/\/doi.org\/10.1109\/IEEESTD.2022.9870098\">https:\/\/doi.org\/10.1109\/IEEESTD.2022.9870098<\/a><\/p>\n\n\n\n<p><strong>[13]&nbsp; <\/strong>IEEE: <em>IEEE Standard for Local and Metropolitan Area Networks \u2013 Forwarding and Queuing Enhancements for Time-Sensitive Streams (Credit-Based Shaper)<\/em>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; IEEE Std 802.1Qav-2009&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <a href=\"https:\/\/doi.org\/10.1109\/IEEESTD.2010.5390974\">https:\/\/doi.org\/10.1109\/IEEESTD.2010.5390974<\/a><\/p>\n\n\n\n<p><strong>[14]&nbsp; <\/strong>IEEE: <em>\u201cIEEE Standard for Local and Metropolitan Area Networks \u2013 Enhancements for Scheduled Traffic (Time-Aware Shaper \/ TSN)\u201d<\/em>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; IEEE Std 802.1Qbv-2015&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <a href=\"https:\/\/doi.org\/10.1109\/IEEESTD.2016.7479742\">https:\/\/doi.org\/10.1109\/IEEESTD.2016.7479742<\/a><\/p>\n\n\n\n<p><strong>[15]&nbsp; <\/strong>AVNU Alliance: <em>\u2018Milan: A Pro AV Standard Based on AVB\/TSN \u2013 Milan Specification\u2019<\/em>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; AVNU Alliance \/ Milan Open Specification&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <a href=\"https:\/\/www.milanspec.org\">https:\/\/www.milanspec.org<\/a><\/p>\n\n\n\n<p><strong>RTP \/ Network Transport<\/strong><\/p>\n\n\n\n<p><strong>[16]&nbsp; <\/strong>H. Schulzrinne, S. Casner, R. Frederick, V. Jacobson: <em>\u2018RTP: A Transport Protocol for Real-Time Applications\u2019<\/em>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; IETF RFC 3550, July 2003&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <a href=\"https:\/\/datatracker.ietf.org\/doc\/html\/rfc3550\">https:\/\/datatracker.ietf.org\/doc\/html\/rfc3550<\/a><\/p>\n\n\n\n<p><strong>[17]&nbsp; <\/strong>H. Schulzrinne, S. Casner: <em>RTP Profile for Audio and Video Conferences with Minimal Control<\/em>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; IETF RFC 3551, July 2003&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <a href=\"https:\/\/datatracker.ietf.org\/doc\/html\/rfc3551\">https:\/\/datatracker.ietf.org\/doc\/html\/rfc3551<\/a><\/p>\n\n\n\n<p><strong>Dante \/ Audinate<\/strong><\/p>\n\n\n\n<p><strong>[18]&nbsp; <\/strong>Audinate Pty Ltd: <em>Dante Audio Networking \u2013 Technical Overview and Whitepapers<\/em>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Audinate, https:\/\/www.audinate.com\/resources&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <a href=\"https:\/\/www.audinate.com\/resources\">https:\/\/www.audinate.com\/resources<\/a>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (Manufacturer reference \u2013 not an open standard)<\/p>\n\n\n\n<p><strong>CERN White Rabbit Project<\/strong><\/p>\n\n\n\n<p><strong>[19]&nbsp; <\/strong>M. Lipi\u0144ski, T. W\u0142ostowski, J. Serrano, P. Alvarez: <em>\u2018White Rabbit: a PTP Application for Robust Sub-Nanosecond Synchronization\u2019<\/em>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ISPCS 2011, IEEE, September 2011&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <a href=\"https:\/\/doi.org\/10.1109\/ISPCS.2011.6070148\">https:\/\/doi.org\/10.1109\/ISPCS.2011.6070148<\/a><\/p>\n\n\n\n<p><strong>Line array acoustics<\/strong><\/p>\n\n\n\n<p><strong>[20]&nbsp; <\/strong>M. Ureda: <em>\u2018Line arrays: Theory and Applications\u2019<\/em>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; AES Preprint 5304, 110th AES Convention, Amsterdam, May 2001&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <a href=\"https:\/\/www.aes.org\/e-lib\/browse.cfm?elib=9888\">https:\/\/www.aes.org\/e-lib\/browse.cfm?elib=9888<\/a><\/p>\n\n\n\n<p><strong>[21]&nbsp; <\/strong>Gunness, D. and Tenney, W. <em>Optimized Polar Patterns for Steerable Arrays<\/em>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; AES Preprint 6757, 121st AES Convention, San Francisco, 2006&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <a href=\"https:\/\/www.aes.org\/e-lib\/browse.cfm?elib=13853\">https:\/\/www.aes.org\/e-lib\/browse.cfm?elib=13853<\/a>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (Reference for waveguide tolerance and phase coherence in line arrays)<\/p>\n\n\n\n<div style=\"height:100px\" aria-hidden=\"true\" class=\"wp-block-spacer\"><\/div>\n\n\n\n<div style=\"background:#f8f8f6; border-left:4px solid #888; padding:1rem 1.25rem; margin:2rem 0;\">\n  <p style=\"font-size:12px; font-weight:600; color:#666; margin:0 0 0.4rem; letter-spacing:0.05em;\">HOW TO CITE<\/p>\n  <p style=\"font-size:14px; color:#222; margin:0 0 0.4rem; line-height:1.6;\">\n    Felusch, B. (2026). <em>Network Precision | Audio-over-IP as a Signal Source for Line Array Speaker Systems.<\/em> Zenodo.\n  <\/p>\n  <a href=\"https:\/\/doi.org\/10.5281\/zenodo.20304490\" \n     style=\"font-size:13px; color:#1a6fa8; word-break:break-all;\">\n    https:\/\/doi.org\/10.5281\/zenodo.20304490\n  <\/a>\n<\/div>","protected":false},"excerpt":{"rendered":"<p>Acoustic coherence in the field of tension between waveguide mechanics and network synchronization. v1.1.1. | 2026-04-28 | \u00a9 Bodo Felusch Switch Language Reference: Requirements for the temporal precision of line array loudspeakers The requirements for the design precision of line array loudspeakers are an old hat. The Waveguide is the most precise component. With its help, the energy of the high-frequency drivers becomes as coherent as possible, i.e. phasenlinear, the [\u2026]<\/p>","protected":false},"author":5,"featured_media":9549,"comment_status":"closed","ping_status":"closed","sticky":true,"template":"","format":"standard","meta":{"_glsr_average":0,"_glsr_ranking":0,"_glsr_reviews":0,"_vp_format_video_url":"","_vp_image_focal_point":[],"footnotes":""},"categories":[1],"tags":[38,31,41,46,45,36,42,48,47,44,39,32,35,33,37,34,40,43],"class_list":["post-9515","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-nicht-kategorisiert","tag-asrc","tag-audio-over-ip","tag-beschallungstechnik","tag-clock-follower","tag-clock-leader","tag-dante","tag-drift","tag-gps","tag-grandmaster","tag-jitter","tag-jitter-buffer","tag-line-array","tag-phasenlinearitaet","tag-ptpv2","tag-st2110","tag-synchronisation","tag-systemdesign","tag-wander"],"_links":{"self":[{"href":"https:\/\/felusch.de\/en\/wp-json\/wp\/v2\/posts\/9515","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/felusch.de\/en\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/felusch.de\/en\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/felusch.de\/en\/wp-json\/wp\/v2\/users\/5"}],"replies":[{"embeddable":true,"href":"https:\/\/felusch.de\/en\/wp-json\/wp\/v2\/comments?post=9515"}],"version-history":[{"count":76,"href":"https:\/\/felusch.de\/en\/wp-json\/wp\/v2\/posts\/9515\/revisions"}],"predecessor-version":[{"id":9677,"href":"https:\/\/felusch.de\/en\/wp-json\/wp\/v2\/posts\/9515\/revisions\/9677"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/felusch.de\/en\/wp-json\/wp\/v2\/media\/9549"}],"wp:attachment":[{"href":"https:\/\/felusch.de\/en\/wp-json\/wp\/v2\/media?parent=9515"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/felusch.de\/en\/wp-json\/wp\/v2\/categories?post=9515"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/felusch.de\/en\/wp-json\/wp\/v2\/tags?post=9515"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}